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Blue Pearl Announces Release 6.0 of EDA Software Suite with SystemVerilog and FPGA Enhancements — Demos at DVCon, Feb. 28-29, 2012, Doubletree Hotel, San Jose, California





Santa Clara, CA (PRWEB) February 21, 2012

Blue Pearl Software, Inc, the provider of next generation EDA software that increases designer productivity and design quality, announced that it is shipping Release 6.0 of its EDA software, Blue Pearl Software Suite, for Windows and Linux operating systems. It includes enhancements that improve support for SystemVerilog and VHDL, as well as FPGA design.




Our 6.0 Release improves support for SystemVerilog and VHDL and the FPGA synthesis flow, said Shakeel Jeeawoody, Director of Product Marketing at Blue Pearl. Designers can now mix and match hardware languages in the same design, with language checking that matches their downstream tools.

Blue Pearl Software Suite offers comprehensive RTL analysis, clock-domain crossing (CDC) checks, and automatic Synopsys Design Constraints (SDC) generation for FPGA, ASIC and SOC designs. Its visualization and validation technology gives users immediate feedback for validating automatically generated timing constraints.

To Learn More

Blue Pearl Software Suite will be demonstrated at the Design and Verification Conference (DVCon), Feb. 28-29, in Booth #405, DoubleTree Hotel, San Jose, California.

FPGA designers can learn more about Blue Pearl Software by registering at http://www.bluepearlsoftware.com/fpga/.

Blue Pearl also offers hands-on workshops and software evaluations.

Price and Availability

Release 6.0 of Blue Pearl Software Suite is available now. Please contact sales(at)bluepearlsoftware(dot)com to arrange a demo, or for pricing and upgrade information.

About Blue Pearl Software

Blue Pearl Software, Inc. provides next generation EDA software that uses new and innovative technology to reduce design flow iterations and increase designer productivity early in the digital design flow. Blue Pearl Software Suite checks RTL designs for functional errors and automatically generates comprehensive and accurate Synopsys Design Constraints (SDC) to improve quality of results (QoR) and reduce FPGA and ASIC design risks.

Visit Blue Pearl Software at http://www.bluepearlsoftware.com

Press Contact:

Georgia Marszalek, ValleyPR, LLC for Blue Pearl Software, +1-650.345.7477, Georgia(at)ValleyPR(dot)com

Acronyms

ASIC:

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