ATtiny2313 Frequency Meter: Counting Architecture and Timing Limits

Scope of the stored design

The page at this URL describes a frequency meter built around an ATtiny2313, seven 7-segment displays, and a small number of discrete parts. In the originating project description, the microcontroller is reported to count input pulses for a one-second interval and display the total, with a stated range of 1 Hz to 9,999,999 Hz and 1 Hz display resolution. Those figures are project assertions rather than demonstrated performance: the stored text reports no measurement uncertainty, no comparison against a reference instrument, and no operating-temperature qualification.

The architecture is conventional for a microcontroller frequency counter. Timer/Counter1 in CTC mode is described as the time base, the 8-bit Timer/Counter0 is described as the event counter fed from the T0 pin, and the seven displays are multiplexed in the remaining processor time. What follows examines that arrangement against the device’s own external-clock requirements and identifies the points a reader should check before treating the stated range as a specification.

The one-second gate and the 1 Hz display step

Counting edges for a fixed gate is the standard method for a direct frequency counter, and the arithmetic is transparent. A count of N edges collected in one second corresponds to N Hz, so the displayed value naturally changes in units of 1 Hz. That is display granularity, not accuracy. A time-base error of one part per million at 1 MHz is 1 Hz (CALCULATIONS: 1,000,000 x 1e-6 = 1), the same magnitude as the least significant displayed digit, and the same relative error grows in absolute terms as frequency rises. Gate-interval error therefore maps directly into count error.

The stored description does not quantify the time-base oscillator’s initial tolerance or drift, nor the dead time between the end of one gate and the start of the next. Both matter: an interval that is not exactly one second scales every reading, and an interval that varies from cycle to cycle adds jitter that no display resolution can remove. The 1 Hz step should not be read as 1 Hz absolute accuracy at any point in the range.

External clock limits at the T0 pin

The ATtiny2313 datasheet, revision 2543M-AVR-10/16, “External Clock Source”, pages 80-81, is the primary constraint on this architecture. It states that the T1/T0 pin is sampled once every system clock cycle by the pin synchronization logic, and that an edge detector generates one counter clock pulse for each selected positive or negative edge. The input is therefore sampled rather than counted asynchronously, and the synchronizer and edge detector together introduce a delay of 2.5 to 3.5 system clock cycles before the counter is updated.

The same section sets out the usable ceiling. Each half period of the applied external clock must be longer than one system clock cycle, and for a 50/50 percent duty cycle the external clock must be guaranteed to have less than half the system clock frequency. The document then recommends that the maximum frequency of an external clock source be less than fclk_I/O/2.5, leaving margin for oscillator tolerance and duty-cycle variation. It also states plainly that an external clock source cannot be prescaled: the prescaler drawn for Timer/Counter0 and Timer/Counter1 acts on the internal clkI/O path, not on a signal arriving at the pin. Any division ahead of T0 must be done by external hardware.

Applying the recommendation to a hypothetical 20 MHz system clock yields a maximum recommended external count rate below 8 MHz (CALCULATIONS: 20,000,000 / 2.5 = 8,000,000). That is a derivation from the datasheet rule, not a bench measurement, and it bears directly on the stored page’s headline endpoint. A guaranteed 10 MHz through T0 is not supported by this document at a 20 MHz clkI/O. Reaching 10 MHz would require a faster verified system clock or a different, documented signal path, and no such evidence is present here. The 10 MHz figure is best treated as an unverified project claim pending measurement.

Rebuilding a wide count from an 8-bit timer

Timer/Counter0 is eight bits wide, so it overflows every 256 input edges. The project description’s reconstruction is the usual software extension: an overflow interrupt increments a multiplier, and when the one-second gate expires the result is formed as the multiplier times 256 plus the residual value left in the counter. For a full-scale reading of 9,999,999 the decomposition is 39,062 overflows with a remainder of 127 (CALCULATIONS: 39,062 x 256 = 9,999,872; 9,999,872 + 127 = 9,999,999). The description adds that both counters are reset just before the gate interrupt returns, after which measurement restarts.

This method is sound only if the multiply-and-add operates on a coherent snapshot, and two hazards are inherent to it. If the residual counter value is read after the counter has wrapped but before the overflow interrupt has run, the multiplier is one low while the residual is already small, so the total comes out short by 256. If the overflow interrupt runs between reading the residual and reading the multiplier, the residual belongs to the old period and the multiplier to the new one, so the total comes out long by roughly 256. Avoiding both requires either masking the overflow interrupt around the read or ordering the reads so that a carry is detected and corrected, with attention to whether the overflow flag was still pending. The stored description supplies no firmware listing, and this review makes no claim that the original code resolves the race.

What remains unverified

Several error terms lie outside what the packet can establish. Input duty cycle matters because the half-period requirement is stated for a 50/50 percent waveform; a narrow pulse or a slowly slewing edge can violate the sampling assumption even below the frequency limit. Edge quality – ringing, slow rise time, or superimposed noise – is not addressed, and no input conditioning, hysteresis, or comparator front end is documented. Gate dead time is unreported, so the effective counting interval may differ slightly from one second. Time-base error dominates absolute accuracy at the low end of the range, where a fixed interval error is a larger fraction of a small count.

An evidence-based evaluation path

A reader assessing this design should begin with the datasheet limits rather than the headline range. Confirm the actual clkI/O frequency, verify that the T0 signal meets the half-period and edge-quality requirements across the intended range, and establish how the overflow snapshot is made atomic in whatever firmware is actually used. Comparing the displayed value against a characterized reference at several frequencies, and recording gate dead time and time-base error, would convert the project’s assertions into measured specifications. Related instrumentation write-ups on this site – covering wideband current measurement, a 555-timer-based power sensor, and a semiconductor curve tracer – follow the same pattern: the circuit may be simple, but the measurement chain determines whether the numbers mean anything.