Some high end applications require multiple or critical calculations to be done by the microcontroller. This may lead to cases when the controller enters into wrong or infinite loops. As a result of this, the system either hangs up or gets crashed. The solution to overcome these situations is to automatically reset the system whenever such a situation arises.
The Watchdog Timer is a hardware or software generated timer interrupt which reboots/resets the system in the situations mentioned above. The watchdog timers are also used in cases when you intentionally require resetting the system without any physical interference.
The Watchdog Timer is a special timer which can be enabled in any section of the code and when enabled it ensures that a certain number of instructions execute within a pre-defined time frame. This time frame or the time delay can be configured/set using the registers of the watchdog timer. In case the instructions execute within the time frame, watchdog timer needs to be turned off and the program execution continues. However, if the instructions fail to execute within this time frame (this conditions is called time out condition) the entire system reboots thus avoiding any system crash or hang up.
Watchdog Timer in ATmega16:
The Watchdog timer of Atmega16
can be configured by using WDTCR register of AVR microcontroller
. When the time out condition is set, the watchdog timer starts counting clock cycles. The watchdog’s timer is clocked from separate on-chip watchdog oscillator of 1MHz frequency. The time out condition is set by configuring prescaler bits of WDTCR register.
WDTCR (Watch Dog Timer Control Register):
WDTOE (Watch Dog Turn-Off Enable) – The watchdog timer is disabled by configuring WDTOE and WDE bits (explained later in the article).
WDE (Watch Dog Enable) – Watchdog timer is enabled by writing 1 to WDE bit.
WDP [2:0] (Watch Dog Prescaler) bits – These three bits determine the watchdog time out condition. The table below shows prescaler bits combination and their corresponding time out period:
Number of WDT oscillator cycles
Typical Time-out at Vcc=3.0V
Typical Time-out at Vcc=5.0V
How Watchdog Timer works:
The watchdog timer starts when the WDE bit is enabled and prescaler bits are configured for time-out condition. As watchdog timer reaches time-out condition, watchdog timer is reset and generates a pulse of one clock cycle which resets the program counter. When watch dog timer resets the timer, the WDRF (Watch Dog Reset Flag) bit in MCUCSR register is set by the hardware. To disable the watchdog timer following steps must be followed:
1. Set the WDE and WDTOE bits in same clock cycle WDTCR register. The logic one must be written to WDE bit even though it is set to one already.
2. After four clock pulses, write logic 0 to the WDE bit. Otherwise watchdog timer will not be disabled.
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