Irvine, Calif., and Athens, Greece (PRWEB) June 4, 2007
ClariPhy Communications and Helic S.A. today announced details of their joint engineering collaboration over the past 12 months, which has been instrumental in the first-pass success of ClariPhy’s single-chip, 10GBASE-LRM, mixed-signal CMOS transceiver. ClariPhy’s transceiver features a low-power 10G Analog to Digital Converter (ADC) and a Maximum Likelihood Sequence Detection (MLSD) Electronic Dispersion Compensation (EDC) engine.
ClariPhy selected Helic’s EDA tool, VeloceRF, after diligent evaluation. The main requirement was synthesis and modeling of spiral inductors, but ClariPhy’s designers found the Helic tool also valuable as an inductive parasitics (RLCK) extractor. VeloceRF was used to synthesize and model all the inductive content of the chip, including on-chip inductors and several critical, high-speed interconnects. VeloceRF enabled ClariPhy’s designers to optimize circuit performance while minimizing silicon real estate. With inductance accurately calculated by VeloceRF, it was possible to mitigate detrimental effects before tapeout, and achieve excellent performance in first-pass silicon.
ClariPhy recently demonstrated its 10GBASE-LRM integrated circuit (IC) with industry-leading performance at OFC 2007. In response to the demand for a better performing product, ClariPhy has developed an all-digital CMOS solution integrating a low power 10G ADC and MLSD engine. The all-digital architecture overcomes the limitations of analog architectures by utilizing underlying signal recovery algorithms that are proven to be optimal for the application. The result is predictable and stable performance near the theoretical limit.
“We knew from the start of this project that success depended on executing beyond the state of the art in mixed signal IC design,” said Dr. Paul Voois, ClariPhy’s CEO. The engineering collaboration with Helic was instrumental in our first-pass design success. ClariPhy has pioneered the migration to an all-digital 10-Gbit/s PHY, and Helic’s tool allowed us to implement our advanced product architecture with confidence.”
“We greatly enjoyed working with the ClariPhy team and supporting them in this breakthrough design. It was exciting to see VeloceRF being used in a non-wireless application and deliver on the promise for first-pass silicon,” said Sotiris Bantas, vice president of technology at Helic. “ClariPhy came to us with a demanding set of requirements, which was understandable considering their very ambitious product architecture. They leveraged the tool’s capabilities and latest features, including spiral component synthesis in CMOS and inductance/mutual inductance extraction for accurate 10 GHz simulations. ClariPhy is already a marquee customer for us, demonstrating VeloceRF as a winning methodology for high-speed and RF nanoscale CMOS design.”
About Helic’s VeloceRF
Helic’s EDA tool, VeloceRF features an inductor synthesizer, the Spiral Wizard, a rapid vector-based RLCK modeling engine, the VeloceRaptor and a powerful methodology to support layout-vs.-schematic verification for any type of integrated inductive component. The tool efficiently addresses DFM requirements emerging for RF CMOS at the 90-nm process node and beyond. Features such as conductor track slotting to mitigate metal stress, geometry resizing under current density constraints and the use of dummy fill patterns, are programmed in the VeloceRF inductor library and are consistently supported by the Spiral Wizard, the modeling engine and the layout and LVS modules.
The Spiral Wizard synthesis engine supports the creation of patterned shields to enhance inductor quality factor (Q) and improve substrate isolation. Generated inductor layouts are fully parametric and DRC-clean by design, easing adoption by foundries and design teams. VeloceRaptor, the rapid, vector-based RLCK modeling engine features a proprietary broadband skin-effect model, with demonstrated accuracy even above 30 GHz. The engine’s speed is class-leading, and outperforms commercial EM simulators and shape-based extraction tools. Built-in netlist reduction keeps netlist sizes and simulation times at reasonable levels, without loss of model precision. Additional information on VeloceRF is available at: http://www.helic.com/products/VeloceRF.
Helic specializes in the development of enabling EDA technologies for RFIC and systems-in-package (SiP) design. Helic’s VeloceRF is the leading EDA tool for integrated inductor synthesis, modeling and verification and has been adopted by several renowned semiconductor companies worldwide. With a global reach and sales offices in Europe, the U.S., and Japan, Helic offers its customers EDA tools, intellectual property (IP) and services that enable delivery of first-pass silicon, while greatly reducing the development cycle for complex wireless transceiver products. Helic is headquartered in Athens, Greece. For additional information please visit Helic at http://www.helic.com or call +302109949390.
ClariPhy Communications, Inc. is a fabless semiconductor company developing high-speed ICs targeting 10G networks in enterprise backbone and enterprise data center environments. ClariPhy’s ICs enable IT management to significantly improve enterprise network performance and lower cost. ClariPhy has secured Series A financing led by Norwest Venture Partners (NVP), with participation from Onset Ventures, Allegis Capital and Pacific General Ventures. ClariPhy has executive offices in Irvine, California and a development center in Cordoba, Argentina. For more information, please visit http://www.clariphy.com.
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