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ClariPhy Leverages Helic’s VeloceRF EDA Tool For First-Pass Success of CMOS 10G Mixed-Signal IC

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Irvine, Calif., and Athens, Greece (PRWEB) June 4, 2007 ClariPhy Communications and Helic S.A. today announced details of their joint engineering collaboration over the past 12 months, which has been instrumental in the first-pass success of ClariPhy’s single-chip, 10GBASE-LRM, mixed-signal CMOS transceiver. ClariPhy’s transceiver features a low-power 10G Analog to Digital Converter (ADC) and a […]

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Helic’s VeloceRF is Selected by Fujitsu to Build RFIC Design-flow for Sub-100nm CMOS Processes

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Athens, Greece (PRWEB) June 4, 2007 Helic S.A. proudly announces that Fujitsu Limited has adopted VeloceRF and Helic’s technology to build a new design-flow for RFICs in its 90nm and 65nm CMOS processes. The parties have agreed to develop world-class tooling and design methodology to support rapid prototyping and volume production of high-frequency ICs applying

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