I2C – Everything you need to know

Two wires, one resistor, nobody drives the high level

I2C uses two wires and no chip selects: devices share SDA and SCL and are told apart by address. Both lines are open-drain. A device can pull a line low through an N-channel MOSFET and can release it, but it cannot drive it high — the pull-up resistor does that, and it is the only thing that does.

That gives wired-AND behaviour: any device pulling low wins, and the line is high only when every device has let go. Every rising edge is therefore an RC charge through the pull-up and the bus capacitance, not a driven edge.

Sizing the pull-up: a window, not a value

Two constraints bound the resistor from opposite ends. The floor is the sink current a device guarantees while still reading as a logic low: Rp(min) = (VDD − VOL(max)) / IOL, with 3 mA and VOL of 0.4 V in Standard and Fast mode, 20 mA in Fast-mode Plus. The ceiling is rise time: Rp(max) = tr / (0.8473 × Cb), where the constant is ln(0.7/0.3), because I2C measures rise time between 30 % and 70 % of VDD, not 10 % to 90 %.

The budgets are tight. Rise time must be under 1000 ns at 100 kHz, 300 ns at 400 kHz and 120 ns at 1 MHz, and one line is capped at 400 pF (550 pF for Fast-mode Plus). A 4.7 kΩ pull-up on 100 pF gives 0.8473 × 4700 × 100 pF ≈ 398 ns: fine at 100 kHz, over budget at 400 kHz. For 3.3 V, 200 pF and 400 kHz the window is 967 Ω to 1.77 kΩ. Below the floor the low level creeps toward the input threshold; above it, edges round off and receivers sample the wrong bit.

Capacitance is the budget nobody measures: the specification allows about 10 pF per pin, and a metre of cable is easily 100 pF. That is why no maximum bus length is specified — capacitance is the limit, not bit rate.

START, STOP, and the register transaction

A START is SDA falling while SCL is high; a STOP is SDA rising while SCL is high. Between them, bytes travel most significant bit first, data may change only while SCL is low, and it must be stable while SCL is high. Each byte is eight bits plus an acknowledge slot: the receiver pulls SDA low to acknowledge, leaves it high for a NACK. There is no length field and no checksum, so the target must know how many bytes to expect.

write:  START  addr+W  reg  data  data  STOP
read:   START  addr+W  reg  Sr  addr+R  data  NACK  STOP

Most sensors are register machines: the first byte after the address is a register number, and following bytes read or write consecutive registers. A read needs the repeated START because the bus changes direction without an intervening STOP, and it must end with a NACK — an ACK leaves the target holding SDA and the bus wedged.

Seven bits, 128 codes, 16 of them taken

The first byte carries a seven-bit address and the read/write bit. Sixteen of the 128 codes are reserved and cannot belong to an ordinary device:

• 0000 000 general call; 0000 001 the START byte, and the CBUS address when read;
• 0000 01XX reserved for other bus formats;
• 0000 1XX High-speed mode controller code;
• 1111 0XX 10-bit addressing; 1111 1XX reserved, including device ID.

That leaves 112 usable addresses, so 0x00–0x07 and 0x78–0x7F are unavailable — worth checking before trusting a datasheet. Ten-bit addressing extends the space, but many controllers omit it and Linux maps such devices into a separate 0xa000–0xa3ff range.

Two controllers on one bus: synchronisation and arbitration

Both mechanisms fall out of wired-AND. On SCL, a high-to-low transition makes every controller count its low period, and the line stays low until the slowest releases it; the high period is set by whichever finishes first. The bus clock is the longest low and the shortest high of the contenders.

Arbitration happens on SDA while SCL is high. A controller sending a one releases SDA and reads it back; if another drives a zero it reads zero, loses arbitration and stops driving. No information is destroyed, and the loser may retry once the bus is idle. Single-controller systems need neither mechanism.

Clock stretching is separate and optional: a target may hold SCL low to buy time. Most targets have no SCL driver, but the ones that can will hang a controller that never checks the clock line after releasing it.

Failure modes that actually happen

• Stuck bus. A target interrupted mid-byte can hold SDA low indefinitely. The bus-clear procedure is nine clock pulses on SCL — nine because a frame is eight data bits plus an acknowledge. If SCL is stuck there is no protocol-level recovery: hardware reset or power cycle only.
• Wrong pull-up. Usually too weak, inherited from a 5 V design, failing only at 400 kHz or at temperature. Several breakouts with 4.7 kΩ resistors put them in parallel, so the effective value is nobody’s decision.
• Address clash. Two devices on one address both acknowledge, and during a read both drive SDA; wired-AND turns the result into garbage rather than damage. Fixed-address parts with one A0 pin are the usual culprits.
• Level mismatch. A 5 V pull-up on a 3.3 V part exceeds its input rating even while the bus “works”; the pin’s protection diode becomes the level shifter.

The numbers above come from the documents cited below. Bus capacitance, the pull-up window on your own board and the survival of a marginal edge across temperature have to be measured on assembled hardware.

References

• NXP Semiconductors, UM10204 — I2C-bus specification and user manual, Rev. 7.0, 2021 (bus protocol, electrical characteristics, bus clear in §3.1.16).
• Texas Instruments, I2C Bus Pullup Resistor Calculation, application report SLVA689, February 2015.
• NXP Semiconductors, AN10216-01 — I2C Manual, 2003.