125 kHz RFID Reader Based on ATtiny13: Version-Bound Design Notes

The tank circuit is the reader

A 125 kHz reader is four blocks: a driver, a resonant tank, an envelope detector and a decoder. The tag has no battery and no transmitter, so what it says arrives as a disturbance in the reader’s own field.

Coil and parallel capacitor form the tank; resonance is f0 = 1/(2π√(LC)). At 125 kHz, LC must sit near 1.62 × 10^-12, so a 410 µH coil — the value EM Microelectronic uses in its EM4095 note — needs about 3.9 nF, and 1 mH about 1.6 nF. The tank also multiplies drive voltage by Q: TEMIC’s U2270B notes give B = f0/Q and UR = Q · UDRV, and their demo coil at Q ≈ 12 reaches roughly 130 V_PP. The detector therefore faces a carrier above a hundred volts.

Q cuts both ways. At Q = 12 the bandwidth is about 10 kHz, ample for 1953 bps; at Q = 50 it is 2.5 kHz and the tank fights the modulation it exists to pass, because recovery between states slows as damping takes longer. TEMIC recommends 5 to 15, and steel near the coil moves both, so bench tuning is not enclosure tuning.

Load modulation: how the tag answers

The EM4100 datasheet says it plainly: the chip sends its 64 bits by turning a modulation current on and off. It switches an extra load across its own coil in step with the data, and because the coils are coupled, the reader’s coil voltage moves with it. That is amplitude modulation of the reader’s own carrier, imposed by a weakly coupled secondary millimetres across. The effect starts small, shrinks with distance and tilt, and a high-Q tank resists it: the energy that makes the carrier large is what makes the envelope slow.

Pulling a small step off a large carrier

                +------+------+
                |      |      |
 GPIO --[R]-----+      |      |
                |      |      |
                L      C      |
                |      |      +---|>|---+--- R2 ---+--> AIN0
                |      |      D1       |           |
               GND    GND               C1          R3
                                         |           |
                                        GND         GND

The tap must survive the full tank voltage and deliver something a 5 V pin can read. A divider does that, but it scales the modulation by the same factor as the carrier: two per cent of 2 V_PP at the pin is 40 mV sitting on a volt or two of DC.

D1 and C1 form a peak detector whose time constant must be long against the 8 µs carrier and short against the 256 µs half-bit; 10 kΩ with 1 nF gives 10 µs. It must also suppress the 125 kHz ripple, or the comparator fires several times per bit and the decoder sees Manchester nobody sent.

A fixed threshold does not last, because the average drifts with distance and supply. The ATtiny13A’s comparator, with AIN0/AIN1 inputs, can slice inside the MCU, but the threshold still has to come from somewhere, and a divider across the supply is the weakest option.

Manchester and the EM4100 frame

EM4100 parts are mask-programmed for 64, 32 or 16 carrier periods per bit. At RF/64 and 125 kHz that is 1953 bps: 512 µs per bit, 256 µs per half-bit. Manchester places a transition mid-bit, so the receiver resynchronises on every edge, which is why a cheap clock can work — though you still measure a half-bit to know which way the edge went.

The 64-bit frame is the only error check on offer:

• 9 header bits, all logic 1; the parity organisation cannot produce that run.
• 10 rows of 4 data bits plus 1 even row parity bit.
• 4 even column parity bits over the data, including the version bits.
• 1 stop bit, fixed at logic 0.

Forty data bits is ten hex digits. The frame repeats while the tag is powered, 32.8 ms each, so a miss costs one wait. Checking both parities separates real reads from noise.

What fits in an ATtiny13A

1 KB of flash is 512 instruction words, and there are 64 bytes of SRAM. No USI, no UART: the serial block is absent, so an ID leaves over a bit-banged pin. On the die: one 8-bit timer, a 4-channel 10-bit ADC, the comparator, and a factory-calibrated 4.8/9.6 MHz oscillator at ±10%, improvable through OSCCAL.

The frame takes 8 of the 64 SRAM bytes before any timestamp, and Timer0 has no input capture, so bit timing comes from pin-change interrupts or polling. At the default 1.2 MHz a 9600 baud software UART bit is 125 cycles. The ±10% oscillator is tolerable because Manchester resyncs every half-bit; the flash is what hurts, since 512 words must hold decoder, parity, serial writer and configuration.

Why read range falls off so fast

At 125 kHz the wavelength is about 2.4 km, so λ/2π is hundreds of metres away and every reader sits deep in the near field. The field of a small loop falls as the cube of distance, so tag power falls as the sixth power: doubling range costs roughly 64 times the power at the tag. A reader that works at 4 cm will not work at 8 cm however hard you drive the coil.

Field is ampere-turns times area, so a larger coil buys range far more cheaply than more current, and tilt matters because the tag has to catch flux lines. Atmel’s ATA5577 antenna note reports 19–22 cm reads for a 68 × 40 mm card coil at 125 kHz from a bench base station; a microcontroller driving a coil through a transistor is a weaker front end and reads shorter.

Resonance, Q, frame layout and memory sizes above come from the documents below. What a particular coil and comparator will do at a given distance has to be measured on your own build.

References

• Microchip Technology, ATtiny13A Data Sheet, DS40002307.
• EM Microelectronic-Marin, EM4100 Read Only Contactless Identification Device datasheet.
• TEMIC Semiconductors, U2270B Antenna Design Hints.
• EM Microelectronic-Marin, Application Note 403 (EM4095 Q&A).