Stand Alone AVR Programmer

What “standalone” removes from the loop

A standalone AVR programmer needs no host when it runs: the image sits on an SD card or local EEPROM, a button starts the transfer, two LEDs report the result. Everything between opening a terminal and typing avrdude becomes a state machine in a microcontroller.

That decides who can program a board. A production fixture, a service kit in a van, a classroom with twelve boards and one laptop — none want a toolchain installed. They want a button and a pass/fail light. A controller with 2 KB of SRAM cannot hold a 32 KB image, so the design streams from storage one page at a time.

The four signals and the sequence behind the button

SCK   --> PB7   held low at power-up
MOSI  --> PB5
MISO  <-- PB6
RESET -->       driven low to enter programming
VCC   -->       ADC divider, sensing only

Apply power with RESET and SCK low, wait 20 ms, then send Programming Enable, 0xAC 0x53 0x00 0x00. The target echoes $53 on the third byte when in sync; otherwise pulse RESET and retry. Data is clocked in on the rising SCK edge, out on the falling edge.

Flash is written by page: on a 32 KB part the page is 128 bytes, so 256 of them, four bytes on the wire per data byte through Load Program Memory Page (0x40), then Write Program Memory Page (0x4C). tWD_FLASH is 4.5 ms between pages unless the programmer polls, and Chip Erase (0xAC 0x80) sets both arrays to $FF. avrdude drives the same instruction set; a standalone box reimplements it, echo check included.

Keeping SCK inside the target’s specification

The clock limit belongs to the target. The ATmega32 datasheet requires SCK low and high periods longer than 2 CPU cycles below 12 MHz and longer than 3 at or above it, so SCK stays at or under fck/4 for a slow part and fck/6 for a fast one. The avrdude manual puts the same rule as “not higher than 1/4 of the CPU clock frequency” and defaults to a 1 µs period.

A factory ATmega32 runs from its internal 1 MHz RC oscillator, so its ceiling is about 250 kHz. A programmer opening at 1 MHz fails the handshake on a fresh part while working on a 16 MHz board. Default the divider slow — 125 kHz never fails a handshake — and let the user raise it. On the host that knob is -B (a period in microseconds, or a frequency with an Hz/kHz/MHz suffix); -i adds a spin-loop delay between bit transitions for bitbang programmers.

VCC sensing, and what a 12 V-free programmer cannot do

SPI programming is specified over 2.7–5.5 V VCC and needs no programming voltage on RESET: no 12 V rail, no high-side switch. The parallel algorithm specifies an 11.5 V minimum on RESET, and that gap is a capability boundary, not a convenience.

If the target’s SPIEN fuse is unprogrammed, ISP is disabled, and the datasheet states that SPIEN “is not accessible in SPI Serial Programming mode”. You cannot restore ISP over ISP, so a button-operated box cannot recover that part, nor one whose clock fuses select an absent crystal.

Sensing VCC is worth one ADC channel. A divider into the 10-bit converter gives about 4.9 mV per step against a 5 V reference, but that reference is the rail being measured, so the result is ratiometric: fine for “is it powered”, useless as an absolute figure. The internal 2.56 V bandgap makes it absolute. Refuse to program below the rated minimum — a target browning out mid-page leaves half-written flash.

Throughput arithmetic, so the slowness is not a mystery

Every data byte costs four bytes on the wire. A 32 KB image is 1,048,576 bits: 4.2 s at 250 kHz, 1.05 s at 1 MHz. Add 256 page writes at 4.5 ms, 1.15 s if nothing overlaps, and a default-clock part lands near 5 to 6 s.

EEPROM is worse, one byte at a time with tWD_EEPROM of 9.0 ms: a 1 KB array is 9.2 s of waiting. A programmer that rewrites EEPROM every run feels broken.

Intel HEX is ASCII — two characters per byte plus length, address and checksum per 16-byte record — so a 32 KB image arrives as roughly 90 KB of text. The card’s 512-byte block is the natural read size for filling a page buffer.

Where it earns its place, and what it is not

Use it for identical boards carrying one firmware, for field updates where a laptop is unavailable or not permitted, and for fixtures where the operator should not open a terminal.

Do not use it as a development tool. Fuse experiments, reading back a mismatch, terminal mode, scripting a matrix of parts — that belongs on a USB programmer, which reports target voltage, adapts its clock and costs less than the parts for a decent box.

The honest split: instruction codes, 128-byte page, 256-page count, 20 ms power-up wait, 4.5 ms page delay, 2.7–5.5 V range and the SCK-per-CPU-cycle rule are datasheet values for the ATmega32. The 5 to 6 s figure is arithmetic on those values, not a measurement. Whether a given target accepts ISP at all, and how your card and divider behave, a builder has to check on the bench.

References

• Microchip (Atmel), ATmega32(L) Datasheet, 2503H–AVR–03/05 — “Memory Programming”, “SPI Serial Programming”, Tables 105, 114, 115.
• AVRDUDE project, avrdude(1) manual page — -B, -i, ISP clock rule.
• Intel, Hexadecimal Object File Format Specification, Revision A (1988).
• SD Association, SD Specifications Part 1: Physical Layer Simplified Specification.