Summary of ARM CoreSight SoC-600, The Future of Debug
CoreSight SoC-600 is ARM’s next-generation debug and trace solution that enables debug and trace over functional interfaces (USB, PCIe, wireless), increasing data bandwidth and enabling remote and lifecycle-wide debug access. It features a new Debug Access Port (DAP) architecture with standard APB connectivity allowing multiple DPs and APs, enhanced Embedded Trace Router (ETR) with up to four times previous trace bandwidth and no separate TMC license, and supports protocol hosting on a dedicated CPU for less intrusive, bare-metal debugging.
Parts used in the CoreSight SoC-600:
- CoreSight SoC-600 IP
- Debug Access Port (DAP) architecture
- Access Port (AP)
- Debug Port (DP)
- APB connectivity
- Embedded Trace Router (ETR)
- Trace Memory Controller (TMC) replacement (integrated functionality)
- Interface peripherals such as USB
- Interface peripherals such as PCIe
- Wireless interface support
- Dedicated CPU for protocol hosting (optional)
Debugging is an important part of the design process that is necessary to identify and fix errors. Over the decades, debug tools had evolved providing easier and simpler solutions. Today, ARM introduces CoreSight SoC-600 as the next-generation debug and trace tool that speeds up finding the root of the problem, with less iterations and lower risks.
Addressing the requirements of the increasingly connected world characterized by faster product-development cycles, this new technology offers debug and trace over functional interfaces such as USB, PCIe or wireless, reducing the need for hardware debug probes while increasing data throughput.
Key benefits include:
- Debug access available and accessible throughout the product lifecycle, from production and manufacture, to remote access in the field
- Remote debug access (e.g. via Ethernet or wirelessly)
- Increased data bandwidth for improved system visibility
- Multiple debug agents can simultaneously access debug memory space (e.g. for concurrent external and self-hosted access)
- Interface peripherals (such as USB and PCIe) share a common access to APs, together with any existing JTAG DP or resident software
- Self-hosted, cross CPU debug access
CoreSight SoC-600 comes with a new Debug Access Port (DAP) architecture. It introduces standard APB connectivity between Debug Port (DP) and Access Port (AP), making it possible to have multiple DPs connected to multiple APs.
CoreSight SoC-600 also includes an enhanced Embedded Trace Router (ETR) functionality. In additional to removing the need for a separate Trace Memory Controller (TMC) license, enhancements to the Embedded Trace Router (ETR) configuration make it possible to supply a trace interface with four times the amount of bandwidth previously possible.
There are two approaches to host the link protocol when building a CoreSight SoC-600-based system:
- Protocol on dedicated CPU: this approach comes at a cost of additional dedicated resources, however, it is the least intrusive approach and provides bare metal debug capabilities.
Read more: ARM CoreSight SoC-600, The Future of Debug
- What is CoreSight SoC-600?
CoreSight SoC-600 is ARM's next-generation debug and trace solution that enables debug over functional interfaces and improves trace bandwidth and remote access. - Can CoreSight SoC-600 provide remote debug access?
Yes, the article states it supports remote debug access via interfaces such as Ethernet or wirelessly. - Does CoreSight SoC-600 increase trace bandwidth?
Yes, enhancements to the Embedded Trace Router make it possible to supply a trace interface with four times the amount of bandwidth previously possible. - How does CoreSight SoC-600 connect DPs and APs?
It introduces standard APB connectivity between Debug Port (DP) and Access Port (AP), allowing multiple DPs connected to multiple APs. - Can multiple debug agents access debug memory concurrently?
Yes, the article says multiple debug agents can simultaneously access debug memory space for concurrent external and self-hosted access. - Does CoreSight SoC-600 remove the need for a TMC license?
Yes, including ETR enhancements removes the need for a separate Trace Memory Controller license. - What interfaces can be used for debug and trace with CoreSight SoC-600?
Functional interfaces such as USB, PCIe, and wireless can be used for debug and trace. - Is there an option to host the link protocol on a dedicated CPU?
Yes, one approach is protocol on a dedicated CPU, which is less intrusive and provides bare metal debug capabilities.
