DIY AVR Development Board with Atmega128

The part choice sets the power supply

The ATmega128 is a 5 V part unless you deliberately buy the low-voltage variant: the ATmega128 is specified for 4.5–5.5 V at 0–16 MHz, the ATmega128L for 2.7–5.5 V but only to 8 MHz.

Decoupling decides whether the ADC is usable. AVR042 asks for one capacitor per VCC/GND pin pair, 100 nF on AVCC and on AREF, AVCC fed through a ferrite from VCC, and 10 µF of bulk at the regulator. The capacitors at the pins supply the 16 MHz current spikes; the regulator is too slow and too far away.

Crystal, load capacitors and CKOPT

On XTAL1 and XTAL2, AVR042 gives 22–33 pF for standard high-frequency crystals; the correct value is roughly twice the crystal’s load capacitance minus pin and stray capacitance. The two capacitors must be equal — AVR042 warns that an unbalanced load shifts frequency and distorts duty cycle — and their ground returns must be short, to the pin beside the crystal.

CKOPT adds internal load capacitors in parallel with the external ones, so read that part’s table. A new chip runs on its internal RC oscillator in ATmega103 compatibility mode, which is why a fresh board looks dead. CKSEL and SUT select the crystal; setting them for a crystal that is not oscillating leaves a part that ignores the programmer, recoverable only by injecting a clock into XTAL1.

Reset, ISP and JTAG

RESET is active low and must be held for the minimum pulse width in the datasheet’s DC characteristics, even with no clock running. AN2519 gives a 4.7 kΩ pull-up to VCC and 100 nF to ground; AVR042 adds that the pull-up must be weak enough for a programmer to pull the line low.

The ISP header carries PB1 (SCK), PB2 (MOSI), PB3 (MISO), RESET, VTG and ground. SCK must be slow when the target is slow: on the factory 1 MHz RC clock the part stays silent at normal programmer speeds. PEN, internally pulled high, is held low through a power-on reset to select SPI programming.

JTAG is PF4 TCK, PF5 TMS, PF6 TDO, PF7 TDI. With JTAG enabled the pull-ups on PF4, PF5 and PF7 stay active even during reset, so those ADC channels do not read cleanly; Microchip also requires TCK below a quarter of the target clock. Fit both headers.

RS-232 needs a transceiver, not a divider

USART0 is on PE0/PE1, USART1 on PD2/PD3. RS-232 levels are inverted relative to TTL and swing to at least ±3 V, often ±8 V; a divider supplies neither the polarity nor the negative excursion. The MAX232 runs from 5 V and builds its levels with a charge pump using four capacitors that TI specifies as 1 µF, for a typical ±9 V output. At 3.3 V use the MAX3232 with 0.1 µF parts. Keep the pump and its switching ripple away from the crystal and AVCC.

Breakouts, and the memory bus that changes the layout

53 I/O lines in a 64-lead TQFP on 0.8 mm pitch: label every header pin with its port name and alternate function; PD2 is also RXD1 and INT2.

The external memory interface takes more pins than anything else: Port A becomes AD7:0, the multiplexed low address and data bus, Port C becomes A15:8, PG2 is ALE, and PG1 and PG0 are /RD and /WR. The low address byte needs an octal latch, typically a 74×573, transparent while ALE is high.

PA0..PA7 ──┬────────────── SRAM D0..D7
           └── 74x573 D ─── SRAM A0..A7
PG2 (ALE) ──── 74x573 G
PC0..PC7 ───────────────── SRAM A8..A15
PG1 (/RD) ──────────────── SRAM /OE
PG0 (/WR) ──────────────── SRAM /WE

The datasheet states that above 8 MHz at 4 V and 4 MHz at 2.7 V the old-style 74HC latch is inadequate for XRAM timing. SRE in MCUCR enables the interface; XMCRA and XMCRB set wait states and the bus keeper, and XMM2:0 releases unused Port C pins. Nineteen traces leave the part for that bus, so decide early whether the SRAM is fitted or the bus broken out.

At first power-up the part is in ATmega103 compatibility mode, where Port C is output only and not tri-stated at reset — anything on Port C is driven low before your firmware runs. Clearing M103C is step one, but the board must tolerate that state.

Bring-up order, cheapest mistakes first

1. Unpowered: VCC-to-ground continuity, capacitor polarity, pin 1 orientation, bridges between adjacent pins.
2. Current-limited 5 V: a working part on its internal RC clock draws very little, so a reading near the limit means a short.
3. VCC at every supply pin, then AVCC, then RESET at VCC — if it is low, a programmer or a bridge is holding it.
4. Read the device signature at the programmer’s slowest clock. Failure is usually SCK too fast, RESET not released, or MOSI and MISO swapped.
5. Confirm the crystal oscillates before changing a clock fuse, and keep a way to inject a clock into XTAL1.
6. Switch to the crystal, blink an LED from a timer, then re-test ISP at the new rate.
7. Transceiver loopback, then an external-memory walking-bit test, then the ADC against a known voltage at AREF.

The fuse steps come last because they are the only ones you cannot undo from the header.

These values come from the ATmega128 datasheet and Microchip’s design notes: they describe what those documents require, not measurements of a built board. Capacitor values, fuse settings and supply behaviour must be checked against the exact ordering code, crystal and programmer in hand.

References

• Microchip, ATmega128/L Datasheet, 2467X–AVR–06/11.
• Microchip, AVR042: AVR Hardware Design Considerations, Atmel-2521.
• Microchip, AN2519: AVR Microcontroller Hardware Design Considerations, DS00002519.
• Texas Instruments, MAX232 Dual EIA-232 Drivers and Receivers, SLLS047.