RISC-V Leader brings unmatched advanced 64-bit Core IP capability to embedded space.
SiFive, the leading provider of commercial RISC-V processor IP, yesterday announced the launch of the S2 Core IP Series at the Linley Spring Processor Conference in Santa Clara. The S2 Core IP Series is a 64-bit addition to SiFive’s 2 Series Core IP and brings advanced features to SiFive’s smallest microcontrollers. The S2 Series further adds to SiFive’s extensive, vastly customizable, optimized, silicon-proven, embedded core IP portfolio, which comprises the 2, 3, 5, and 7 Core IP Series in E (32-bit) and S (64-bit) variants.
Edge SoCs face the diverse requirements of real-time latency, deterministic capability and stringent power constraints. The S2 enables SoCs to have an always-on low power CPU that can be combined with high-performance CPUs that switch on only when applications demand performance, such as in voice-activated smart devices. The 2 Series can be configured to be as small as just 13,500 gates (in RV32E form). The S2 is just half the size of a similarly configured S5 core. Security is enhanced by separation between secure and non-secure domains. This degree of flexibility is what is needed to meet the constraints in terms of power, area and real-time demands as well as the requirements in terms of performance of modern edge workloads and applications. The S2 Series will be available as a customizable Core IP Series as well as in the form of standard cores via SiFive’s Core Designer.
SiFive’s 64-bit S Cores bring their hallmark efficiency, configurability and silicon-proven Core IP expertise to 64-bit embedded architectures,
said Ted Speers, head of product architecture and planning at Microchip Technology’s Microsemi subsidiary and RISC-V Foundation board member.
The S Cores will enable innovation for the next generation of embedded compute.