Step-by-Step Design Process for the MAX16833 High-Voltage High-Brightness LED Driver


This application note details a step-by-step design process for the MAX16833 high-voltage high-brightness LED driver to speed up prototyping and increase the chance for first-pass success. The MAX16833 is a peak current-mode-controlled LED driver, capable of driving an LED string in several different architectures: boost, buck-boost, SEPIC, flyback, and high-side buck topologies.
The MAX16833 offers several features: a dimming driver designed to drive an external p-channel MOSFET, extremely fast PWM current switching to the LEDs without transient overvoltage or undervoltage, analog dimming, programmable switching frequency between 100kHz and 1MHz, and the option of either a ramp output for frequency dithering or a voltage reference for precisely setting the LED current with few external components.
For the design example in this application note, a 7 LED string is driven with a constant current of 1A. Assume that each LED has a typical forward voltage drop of 3V and a dynamic resistance of 0.2Ω. Also assume that the LED driver circuit is running directly off of the car battery, which has a typical voltage of 12V but can vary from 6V to 16V. Since the LED string voltage is always greater than the input voltage, the boost configuration is chosen.
LED Driver

Inductor Selection (Boost)

In order to select the right inductor value, the maximum duty cycle must be calculated:
(Eq. 1)
Where VLED is the forward voltage of the LED string in volts, VD is the forward drop of the rectifying diode (approximately 0.6V), VINMIN is the minimum input-supply voltage in volts, and VFET is the average drain-to-source voltage of the switching MOSFET in volts when it is on (assume 0.2V initially).
The maximum duty cycle and LED current determine the average inductor current.
(Eq. 2)
The peak inductor current is defined as follows:
(Eq. 3)
Where ΔIL is the peak-to-peak inductor current ripple in amperes.
Finally, the minimum inductor value can be calculated:
(Eq. 4)
Below is a numerical example based on the design problem outlined in the Introduction. Choose an inductor current ripple of 50%. Lower ripple current would require a larger (and typically more expensive) inductor. Higher ripple current requires more slope compensation and increased input capacitance.
(Eq. 5)
(Eq. 6)
(Eq. 7)
(Eq. 8)
Once the minimum inductor value has been determined, a real inductor value must be chosen that is as close to LMIN as possible without going under. Recalculate the peak inductor current and ripple using the chosen inductor value. These numbers are necessary for additional calculations going forward.
(Eq. 9)
(Eq. 10)
(Eq. 11)
Ensure that the chosen inductor has a current rating higher than ILP. Typically, 20% headroom is used for inductor peak current.

Input Capacitor Selection

In a boost converter, the input current is continuous so the RMS ripple current is low. Both bulk capacitance and ESR contribute to the input ripple. Assume equal ripple contributions from bulk capacitance and ESR if aluminum electrolytic and ceramic capacitors are both used in parallel. If only ceramic capacitors are used, most of the input ripple comes from the bulk capacitance (since ceramic capacitors have very low ESR). Use the equations below to calculate the minimum input bulk capacitance and maximum ESR:
(Eq. 12)
Where ΔVQ_IN is the portion of input ripple due to the capacitor discharge.
(Eq. 13)
Where ΔVESR_IN is the input ripple due to ESR.
Assume that a maximum of 120mV of input ripple can be tolerated (2% of VINMIN). Also assume that 95% of this input ripple comes from the bulk capacitance. This assumption may need to be revisited if the calculated values are not easily attained with actual components. Based on the stated design specifications, the input capacitor is calculated as follows:
(Eq. 14)
(Eq. 15)
Use two 4.7µF capacitors in parallel to achieve the 8.5µF minimum bulk capacitance. Ensure that the chosen capacitors meet the minimum bulk capacitance requirement at the operating voltage (capacitance can decrease substantially with a change in voltage in ceramic capacitors).

Output Capacitor Selection

The purpose of the output capacitor is to reduce the output ripple and source current to the LEDs when the switching MOSFET is on. Both bulk capacitance and ESR contribute to the total output voltage ripple. If ceramic capacitors are used, a majority of the ripple comes from the bulk capacitance. Use Equation 16 to calculate the required bulk capacitance:
(Eq. 16)
Where ΔVQ_OUT is the portion of output ripple due to the capacitor discharge.
The remaining ripple, ΔVESR_OUT, comes from the output capacitor ESR, which can be calculated as follows:
(Eq. 17)
To determine the total allowed output ripple, multiply the allowed LED current ripple by the dynamic impedance of the LED string. The dynamic impedance of an LED is defined as ΔV/ΔI at the operating LED current and can be determined from the I-V curve in the LED data sheet. If an I-V curve is not provided in the LED data sheet, then it must be measured manually.
Use multiple ceramic capacitors in parallel to reduce the effective ESR and ESL of the bulk output capacitance.
During PWM dimming, the ceramic output capacitors might cause some audible noise. To reduce this noise, use an electrolytic or tantalum capacitor in conjunction with the ceramic capacitors to provide most of the bulk capacitance necessary. A low acoustic noise ceramic capacitor can also be used.1
Assume a maximum LED current ripple of 0.1 × ILED. Also, assume that the dynamic impedance of the chosen LED is 0.2Ω (1.4Ω total for the 7 LED string). The total output voltage ripple is then calculated as follows:

About The Author

Ibrar Ayyub

I am an experienced technical writer holding a Master's degree in computer science from BZU Multan, Pakistan University. With a background spanning various industries, particularly in home automation and engineering, I have honed my skills in crafting clear and concise content. Proficient in leveraging infographics and diagrams, I strive to simplify complex concepts for readers. My strength lies in thorough research and presenting information in a structured and logical format.

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