Verification

Accellera Approves Updated Property Specification Language Standard for Electronic Design Verification, Begins IEEE Standardization Process

NAPA, CA (PRWEB) August 6, 2004 New Version Aligns Accellera┬ĺs PSL Standard with SystemVerilog Assertions. Accellera, the electronics industry organization focused on electronic design automation (EDA) standards, today announced that its Board of Directors, representing systems, semiconductor and design tool member companies, approved Accellera┬ĺs Property Specification Language (PSL) standard version 1.1 as an Accellera design […]

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PDKChek™ Process Verification IP Introduced for Fabless IC Houses

(PRWEB) December 9, 2004 Fabless Semiconductor Manufacturers rely upon process-dependent data supplied by external Semiconductor Foundries to create accurate and well-centered IC designs. The supplied foundry data is contained in Process Design Kits (PDK┬ĺs). When the actual process variations differ from the PDK┬ĺs, then the ICs will not work properly, if at all. Some Fabless

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Integre Technologies Announces PCIExpress™ Verification Services

Pittsford, NY (PRWEB) September 29, 2005 Integre Technologies a leading provider of ASIC design and verification services today announced their PCIExpress™ verification service. This service is targeted to organizations developing products with the PCIExpress interface. “Our project experience allows us to avoid the pitfalls and risks of various tools and environments” states Mark Blejwas

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ChipX selects nSys Verification Suite (nVS) for PCI Express Verification

Newark, CA (PRWEB) March 2, 2006 nSys Design Systems, the leading Verification IP provider in Verilog for design and verification of semiconductor chip interfaces, today announced that ChipX, the leader in Structured ASIC products and technology, has chosen the nSys Verification Suite (nVS) for PCI Express verification.   ChipX Structured ASICs offers near standard-cell ASIC

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Silicon Interfaces Announces Bluetooth and USB 2.0 OpenVera Assertions-Based Verification Intellectual Property

(PRWEB) December 13, 2002 Silicon Interfaces, a high-end design services provider, today announced the availability of Bluetooth and USB 2.0 verification intellectual property (IP) offerings based on OpenVera(TM) Assertions (OVA). These easy-to-use OVA verification IP solutions significantly reduce the time necessary to create the verification infrastructure and automated testbench environment required for verifying complex Bluetooth

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VWorks Exhibits at DVCon 2012: The Design and Verification Conference

SAN JOSE, CA (PRWEB) February 28, 2012 VWorks is exhibiting at DVCon 2012, the premier conference for functional design and verification, at Booth #503.   WHO: VWorks: Advancing the Technology of Electronic System Design.   WHAT: VWorks exhibits new technology and services to accelerate ESL design, for electronics hardware, embedded software and systems at DVCon

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VIDEOTEK’S ULTIMATE SOLUTION: SIGNAL QUALITY MANAGERThe Only Solution for Enterprise Management of Signal Verification in a Centralized Environment

(PRWEB) September 6, 2002 Monitoring the quality of television signals in multi-channel facilities has traditionally been time consuming, expensive and inefficient. An increasing number of broadband, satellite (DBS and uplink facilities), data path and content providers, and even traditional broadcasters are faced with growing numbers of channels/services, sources, and system path points to monitor. In

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