ATxmega32A4U DACB: Two 12-Bit Channels, Output Pins, and Calibration Conditions

What DACB is, and which parts have it

On XMEGA A and AU devices the converter sits on port B, and the manual is explicit about the naming: “PORTB has one DAC. Notation of this peripheral is DACB.” On an ATxmega32A4U the outputs are PB2 (DAC0) and PB3 (DAC1), with the external reference input on PB0, marked AREF. Twelve-bit resolution, two channels, one conversion block, up to 1 Msps in single-channel operation.

One correction first: the XMEGA D manual (Atmel-8210G) has no DAC chapter, and D-series parts list no DAC. Everything below is from the XMEGA A manual, section 26, and the A4U datasheet.

Two channels, one converter

One conversion block sits behind both channels. CTRLB.CHSEL = 0x00 is single-channel mode: the block is wired permanently to channel 0 with the sample-and-hold stage bypassed, giving a continuous-drive output. 0x02 is dual mode: the block alternates between channels while two sample-and-hold stages hold the results.

That alternation costs time. The manual requires at least 1 µs between conversions in single-channel mode and 1.5 µs in dual mode, and caps the sample-and-hold refresh interval at 30 µs. TIMCTRL.REFRESH generates that refresh from the peripheral clock, independently of conversions you trigger yourself.

Data goes in as two bytes; writing the high byte starts the conversion. STATUS.CH0DRE shows the register is free, and writing while it is clear overwrites the pending value. The module has no interrupts.

Choosing the reference

CTRLC.REFSEL selects the internal 1.00 V reference, AVCC, or one of the two AREF pins — PA0 and PB0 on the A4U. A selection that points at a pin your board never wired is the quiet way to get a random output, so fix the reference choice in one place and check it against the schematic.

• Internal 1.00 V — 0.99–1.01 V after calibration, no external part. Costs 1 V of swing and gives the worst linearity at ±5 LSB INL.
• AVCC — widest swing, best INL (±4 LSB at VCC = 3.6 V), but the output is only as stable as the 3.3 V rail feeding it.
• AREF — external reference, 1.0 V minimum to AVCC − 0.6 V maximum; input resistance above 10 MΩ, about 7 pF. This is the option that makes the converter a measuring instrument.

One code is 244 µV against 1.00 V and 806 µV against a 3.3 V AVCC. The manual gives V_DAC = CHnDATA/0xFFF × V_REF, and the linear output range is 0.15 V to AVCC − 0.15 V: both ends of the code range are soft.

The output stage and what it can drive

Each channel has a buffer with feedback to the pin, maximum DC output impedance 50 Ω. The load limits matter:

• Minimum resistive load 1 kΩ.
• Maximum capacitive load 100 pF, relaxed to 1 nF only with 1000 Ω of series resistance.
• AVCC/1000 of sink or source current within the accuracy specification — about 3.3 mA at 3.3 V — and 10 mA for “safe operation”, meaning outside it.

The 100 pF figure is tighter than it sounds: a metre of ordinary coaxial cable is specified around 100 pF, so one bench lead uses the whole budget. The 1 kΩ series resistor buys 1 nF, but 1 kΩ × 1 nF is a 1 µs time constant, and a 12-bit step needs about 8.3 of those — roughly 8 µs, a ceiling near 120 kHz. That is arithmetic on the datasheet limits, not a measurement.

Calibration is a software job

Production test measures offset and gain and stores them in the signature row: DACBOFFCAL at 0x32, DACBGAINCAL at 0x33. Unlike the oscillator calibration these are not loaded automatically; the byte must be copied into the register from software. Both are seven-bit signed-magnitude values, bit 6 for direction, bits 5:0 for magnitude. Output 0x800 and trim offset until the output sits at half the reference, then output 0xFFF and trim gain until it reaches V_REF × 4095/4096, which rotates the transfer function about mid-code. One offset step is 1 LSB, one gain step 4 LSB; residual error is specified under 1 LSB offset and 4 LSB gain.

DACB.CTRLB       = DAC_CHSEL_SINGLE_gc;   /* continuous drive, channel 0 */
DACB.CTRLC       = DAC_REFSEL_INT1V_gc;   /* 1.00 V ref, right-adjusted */
DACB.CH0GAINCAL   = sig_read(0x33);       /* DACBGAINCAL */
DACB.CH0OFFSETCAL = sig_read(0x32);       /* DACBOFFCAL  */
DACB.CTRLA       = DAC_CH0EN_bm | DAC_ENABLE_bm;

while (!(DACB.STATUS & DAC_CH0DRE_bm)) { }
DACB.CH0DATAL = value & 0xFF;             /* low byte first */
DACB.CH0DATAH = (value >> 8) & 0x0F;       /* high byte starts conversion */

Control voltage or audio

As a control voltage it is pleasant. A setpoint into an op-amp input, a comparator threshold, or an ADC channel is a load above 1 kΩ and costs nothing; 50 Ω of source impedance is irrelevant at DC. The caveats are the 0.15 V dead zones — a zero command does not give you ground — and the 3.3 mA limit, which rules out relay coils and low-value dividers without a buffer. CTRLA.IDOEN routes channel 0 to the internal comparator and ADC and disables the pin.

As an audio source it is workable and limited. Twelve bits is 74 dB of theoretical signal-to-noise, enough for a demonstration, but there is no reconstruction filter, no sample clock, and no output that survives a cable. Audio needs a timer or event channel triggering at a fixed rate, DMA feeding CH0DATA so timing does not jitter, AC coupling to escape the dead zones, and an external buffer. In dual mode the 1.5 µs floor still allows stereo at 44.1 kHz — 22.7 µs per sample pair — but refresh and DMA demand must be configured deliberately.

The register names and limits above come from the documents below. A builder must still establish the reference voltage of their part, the real load their circuit presents, and whether the signature-row calibration values improve linearity on that individual device — the datasheet specifies residual error, not the direction of the change.

References

• Microchip, AVR XMEGA A Manual, 8077I–AVR–11/2012 — section 26, “DAC – Digital to Analog Converter”; section 4.17, production signature row.
• Microchip, ATxmega128/64/32/16A4U Data Sheet, DS40002166A — section 29, Table 32-2, Tables 36-12 to 36-14.
• Microchip/Atmel, AVR1301: Using the XMEGA DAC, 8033B–AVR–04/08.
• Microchip, AVR XMEGA D Manual, Atmel-8210G–AVR XMEGA D–12/2014 — module list, for the absence of a DAC chapter.