Logic Analyzer Basics: Acquisition Windows, Triggers and Timing versus State

Scope and historical example

The Embedded Lab tutorial by R-B, dated 25 January 2013, uses the IKALOGIC SCANALOGIC-2 educational kit to introduce basic logic analyzer features. That tutorial describes the kit as a four-channel board reported at 20 million samples per second, with 256K samples of memory per channel and decoding for I2C, SPI, UART and 1-Wire. Those are historical reported features, not measured capabilities, and the kit manual is not part of the evidence here.

What the instrument records

A logic analyzer captures many signals at once and displays their timing relationships, which is why it suits timing violations and transients on buses. In timing mode each channel stores a logic state at fixed intervals. The interval is the reciprocal of the sample rate, so 1 MS/s gives one sample per microsecond, and every other quantity in the capture is derived from that grid. Analog detail such as rise time, overshoot and noise is discarded, so a reader who needs edge shape rather than logic level is asking a question closer to a bandwidth-limited analog measurement.

An edge is therefore located by convention rather than observed. If the ideal transition falls inside a sample interval of length Ts, the analyzer reports the first sample taken after it, so the recorded edge time is late by an amount in the interval from zero up to but not including Ts.

An interval between two recorded edges accumulates one such delay at each end. Since each is independently somewhere in [0, Ts), the measured interval differs from the true interval by an amount between -Ts and +Ts. Quoting a single figure near plus or minus one sample as the edge error merges two quantities: edge timestamp error is one-sided, while a two-edge interval carries the wider bounded error.

Timing mode and state mode

In timing mode the analyzer samples at regular intervals on its own internal clock, with no fixed phase relationship to the target, which makes the mode asynchronous and suited to edge placement, skew between lines, and how close a data transition falls to a clock edge. In state mode a signal from the target, usually its clock, defines the sample point, and signals are captured on the active edge of each clock received. Relative timing between signals then matters less than the sequence of states presented, one entry per clock.

State mode is not a finer timing mode; it answers a different question. A state capture shows values in order and says nothing about margin, while a timing capture of the same traffic exposes where transitions sit relative to the clock. For period or pulse-width questions rather than bus content, a dedicated counter such as the AVR frequency meter is the better instrument.

Sizing an acquisition window

Stored samples equal sample rate times window duration. The tutorial illustrates it with its own case: a 32K-deep analyzer at 1 MS/s fills in 32 ms.

On a generic 100 kHz I2C bus one SCL period is 10 us, a byte is eight data bits plus an acknowledge, so nine clock pulses or 90 us, and a three-byte frame of device address, register address and data is 27 clocks or 270 us (derived; CALCULATIONS.json:9179 generic_27_clocks_at_100kHz_s). A register-based sensor such as the BH1750FVI light meter would present traffic of that general shape; the sequence here is generic, not that device’s protocol. With 100 us of pre-trigger and 100 us of post-trigger the window is 470 us, rounded to 500 us, which at 1 MS/s holds 500 samples per channel and ten per SCL period (derived from the stated inputs).

Sampling rate and aliasing

Plausible samples do not prove the signal behaved as drawn. When the sample rate is an exact multiple of the signal frequency, consecutive samples can land at the same phase of every cycle. A 1 MHz clock sampled at exactly 1 MS/s returns one sample per clock period at a fixed phase, so eight samples across an 8 us transfer can all read the same level although the clock toggled eight times (derived; CALCULATIONS.json:9179 alias_same_phase_samples). That result fits both a running clock and a stopped one, and it is not evidence of activity.

Sample several times faster than the fastest feature of interest, and do not assume an integer ratio between sample rate and clock frequency is safe. A 2 ms window at 1 MS/s holds 2,000 samples per channel (derived; CALCULATIONS.json:9179 samples_2ms_1MSps), which is the memory cost of that choice, fixed before any measurement.

Triggering and pre-trigger depth

A trigger is a logic condition on the sampled data that must be met before recording starts, and memory is finite, so the trigger is what places the action inside the window. Simple conditions include a change of state on one line, a specific value on a bus, or a sequence of values; complex conditions are harder because they must be evaluated in real time.

Trigger condition and pre-trigger depth are therefore part of the measurement design. A capture armed after the fault shows the consequence and hides the cause, and for bus work a frame boundary aligns the window with a transaction rather than an arbitrary instant. Which trigger modes and pre-trigger depths the board offers is not established by the tutorial and would need its manual.

Failure modes worth checking

A signal that crawls through the input threshold band can be latched differently from sample to sample, producing edges the target never generated; a slow open-drain rise is the usual cause. Threshold behaviour and any optional digital filter belong to the specific model, and a filter is not a free fix: it removes narrow pulses, including real ones. Edge quality is assessed before a filter is enabled, with a scope as the reference for edge shape.

A line that never moves is the second case: confirm the pin is driving and the analyzer ground is bonded to the target ground at one point, since a floating input reports whatever its threshold decides. Channel count is the third. The board in the tutorial has four channels, the same tutorial notes that some analyzers carry over 100, and neither number generalises; a wide parallel bus needs different hardware. Input protection ratings are model-specific, so read them from the unit’s own documentation before a probe touches a target and keep the work on extra-low-voltage, isolated supplies.

Untested proposals and evidence gaps

Nothing here was compiled, simulated or measured, and no captures stand behind it. Three items are proposals awaiting test: triggering on the device-address byte to capture one slave’s traffic, repeating a transaction in both state and timing mode to see where margin is lost, and comparing captures with any filter enabled and disabled to test whether suspect edges are real. The kit’s measured sample rate, timing accuracy and input characteristics remain unverified, and whether an analyzer suits a bus depends on that instrument and that bus.