Externally clocking (and overclocking) AVR MCUs

What the clock fuses actually select

An ATmega32 does not start until the fuses say how fast to run. Four bits in the low fuse byte, CKSEL3..0, pick the source: 1111–1010 crystal or ceramic resonator, 1001 a 32.768 kHz watch crystal, 1000–0101 external RC, 0100–0001 the calibrated internal RC oscillator, 0000 an external clock on XTAL1. The part ships with CKSEL = 0001 and SUT = 10 — 1 MHz internal RC, longest start-up — so a programmer can always reach an unconfigured chip.

SUT1..0 set how long reset is held: how many oscillator cycles are counted and whether 4.1 ms or 65 ms is added. CKOPT, in the high fuse byte, switches the crystal amplifier from low-swing, low-power mode to full rail-to-rail drive; unprogrammed, resonators stop at 8 MHz, programmed at 16 MHz.

Internal RC, crystal, external clock

The internal RC oscillator costs nothing and needs no pins. Factory calibration gives ±3% at 5 V and 25 °C on the 1 MHz setting; AVR053 trims it against a reference to roughly ±1%. Frequency moves with supply and temperature, so such a board keeps poor time and its UART needs margin.

A crystal buys tens of ppm for two pins, two equal load capacitors (12–22 pF) and milliseconds of start-up. An external clock drives XTAL1, leaves XTAL2 open and sets CKSEL = 0000: no capacitors, no amplifier, any frequency the source can make. One constraint is easy to skip: the applied frequency must not change by more than 2% cycle to cycle, and the device must be held in reset while it changes — which rules out swapping generators on a running board.

The frequency ceiling follows VCC

The headline numbers mislead. The ATmega32 is specified for 0–16 MHz over 4.5–5.5 V; the ATmega32L for 0–8 MHz over 2.7–5.5 V. Those are the ends of a curve, not two products: the permitted frequency falls as the supply falls. A 3.3 V board with a 16 MHz crystal sits outside the characterised area for both grades; 8 MHz is the number you can defend at 3.3 V.

Below the ceiling there is no minimum. The core is fully static, so a watch crystal runs the same instruction stream 500 times slower. Overclocking is the opposite trade: throughput improves, and nothing the vendor published covers the part.

What breaks first when you push past it

Program fetch. The first symptom is rarely a clean crash. Instruction fetch stops meeting timing: wrong branch targets, spurious resets, code that works cold and fails warm. Nothing reports it — there is no trap for a bit read wrong.

EEPROM and flash writes. The calibrated oscillator times EEPROM and flash access; when writing either, do not calibrate more than 10% above nominal or the write may fail. A half-completed write leaves a byte you did not intend.

USART timing. The divisor is UBRR = fosc/(16 × baud) − 1. At 16 MHz and 115200 baud the ideal is 8.68, so UBRR = 8 gives 111111 baud, about −3.6%, before the other end’s error is counted. U2X halves the divisor and changes the arithmetic, which is why such a board works at one baud rate, not another.

ADC timing. Full 10-bit resolution needs an ADC clock between 50 and 200 kHz, 13 clocks per conversion. The prescaler that was right at 8 MHz is wrong at 16 MHz; leave ADPS alone and resolution quietly drops.

Recovering a board with a dead clock

Set CKSEL = 0000 on a board with nothing driving XTAL1, or select a crystal that was never fitted, and the core never starts. ISP cannot synchronise, and the programmer reports a target that will not enter programming mode. The chip is usually fine.

Feed a square wave into XTAL1: 1 to 4 MHz, from a generator or a spare microcontroller’s clock output. With the core running, ISP works again. The AVRISP guide requires the target clock to be at least four times the programming clock, so slow the programmer down too — -B 10 in avrdude is roughly 100 kHz. Then rewrite the fuse byte.

lfuse:  bit 7     6      5     4     3..0
        BODLEVEL BODEN  SUT1  SUT0  CKSEL3..0

avrdude -c usbasp -p m32 -B 10 -U lfuse:r:-:h      # read it first
avrdude -c usbasp -p m32 -B 10 -U lfuse:w:0xE4:m   # 8 MHz int. RC, SUT=10
avrdude -c usbasp -p m32 -B 10 -U lfuse:w:0xEF:m   # 16 MHz crystal, SUT=10
avrdude -c usbasp -p m32 -B 10 -U hfuse:w:0x89:m   # CKOPT programmed

If SPIEN has been cleared or RSTDISBL programmed, ISP is gone by design and clock injection will not bring it back. The AVRISP guide points at high-voltage parallel or serial programming, or JTAG while JTAGEN is still set — hardware most people do not own, which is the argument for never touching those fuses on a board you care about.

Experiments that stay recoverable

• Socket the crystal, or bring XTAL1 out to a header, so a clock can be injected without desoldering.
• Record the fuse bytes first: avrdude -U lfuse:r:-:h -U hfuse:r:-:h costs a second.
• Run experiments from a current-limited supply, and treat an overclock as a bench result, not a design. An hour at 24 MHz says nothing about the next thousand units.

Everything above comes from the vendor documents listed below. Nothing was measured: the fuse bytes are arithmetic from the datasheet’s bit tables, and a builder should read them back before trusting either.

References

• Microchip Technology, ATmega32/L Datasheet, DS0002503 — “System Clock and Clock Options” and “Speed Grades”.
• Microchip Technology, AVR053: Internal RC Oscillator Calibration for tinyAVR and megaAVR Devices, Atmel-2555.
• Microchip Technology, Atmel AVRISP mkII User Guide, Atmel-42093 — ISP clock ratio and recovery.