Make an Oscilloscope Using the SainSmart Mega2560 with the TFT LCD shield and the 3.5 "color touch screen

ADC timing sets the ceiling before you write any code

The ATmega2560’s 10-bit successive-approximation ADC runs from its own clock domain, divided from the system clock by ADPS2:0 in ADCSRA. The datasheet allows 50–200 kHz of ADC clock for full resolution, spends 13 cycles on a normal conversion and 25 on the first after ADEN, and closes the sample-and-hold 1.5 cycles after the start.

On a 16 MHz Mega, divide-by-128 gives 125 kHz and 104 µs per conversion: 9,615 samples per second. Even at the top of the 10-bit band, 200 kHz, you reach only 15,384.

ADMUX  = (1 << REFS0);              // AVCC reference, channel ADC0
ADCSRA = (1 << ADEN) | (1 << ADATE)
       | (1 << ADPS2) | (1 << ADPS1) | (1 << ADPS0);   // /128
ADCSRB = 0;                         // ADTS = 000: free running
ADCSRA |= (1 << ADSC);              // first conversion: 25 clocks

Free-running mode removes the software start latency, not the 13 cycles. Divide-by-64 doubles the rate to 19.2 kS/s but leaves the 10-bit specification; AVR126 puts the practical floor near 1 MHz, where about 8 bits remain.

Bandwidth, Nyquist and aliasing

9,615 samples per second gives a Nyquist limit of 4.8 kHz. Two samples per cycle prove a sine exists but say nothing about its shape. Ten to twenty samples per cycle draws a recognisable waveform, so the honest viewing range is roughly 500 Hz to 1 kHz. The sample-and-hold aperture, 1.5 clocks or 12 µs at 125 kHz, averages the input over that window and smears fast edges anyway.

Sampling repeats the spectrum every fs. A 20 kHz sine at 9,615 S/s aliases to |20000 − 2 × 9615| = 769 Hz, drawn as a clean, stable 769 Hz sine that nothing in the software can flag as false. Land exactly on twice the sample rate and it folds to DC: a 5 V peak-to-peak signal renders as a flat line.

Only an analog filter ahead of the ADC helps. A single-pole RC at 4.8 kHz — 1 kΩ and 33 nF — attenuates 20 kHz by about 12 dB, nowhere near enough, and a filter steep enough to suppress the alias would remove the signal you wanted to see. That conflict fixes real bandwidth near a kilohertz.

The front end: divide, bias, clamp

The ADC is unipolar: 0 V to V_REF in, 0 to 1023 out. Anything swinging below ground clips and can damage the pin, so the input stage must scale the signal, offset it into range, and survive hostile connections.

• Scaling. A divide-by-four network maps ±5 V to ±1.25 V; a bias shifts that to 1.25–3.75 V.
• Source impedance. The datasheet asks for about 10 kΩ or less so the hold capacitor charges inside its 12 µs window. A 10k/10k divider gives 5 kΩ and works; 1 MΩ reads low and noisy.
• Protection. A 100 Ω series resistor into a dual Schottky clamp to AVCC and ground keeps the pin inside its rails and limits clamp current.

A rail-to-rail buffer fixes the impedance properly if it runs from the same 5 V rail. A 10× scope probe does not work here: it expects 1 MΩ to divide against and compensate, and 5 kΩ gives the wrong ratio.

Software triggering is correct, and coarse

There is no trigger comparator in the chip. The usual method: fill a buffer in free-running mode, find the first upward crossing of mid-code with a couple of LSB of hysteresis, and draw from that index. With 8 KB of SRAM, 1,024 samples at two bytes costs 2 KB.

Trigger resolution is one sample period. At 1 kHz, 104 µs is 37° of phase, so successive sweeps land differently and a stable source shimmers. There is no holdoff and no trigger on slope or pulse width — only “first edge after the buffer start”.

Drawing the trace on a 320×480 panel

These shields use a 16-bit parallel, 8080-style bus: sixteen data lines plus register/data select, write strobe, chip select and reset. You write by setting a column and page window, then streaming pixels into the controller’s GRAM. Two bytes per pixel makes a full 320 × 480 frame 307,200 bytes, so whole-screen redraws per capture are out.

Draw in columns. A 300-pixel plot holds 31 ms at 9,615 S/s, so one column per sample maps naturally: write the new pixel, erase the old one in that column, leave the grid alone. The previous y-value per column fits in 600 bytes.

Identify the controller before writing an init sequence. SainSmart’s 3.2-inch boards used the SSD1289 with an ADS7843 touch controller; 3.5-inch panels in this class are usually ILI9486-compatible at 320 × 480. Touch is a separate SPI device.

Where this stops being an oscilloscope

It is unipolar, so AC coupling is external or absent. One ADC behind a multiplexer means two channels are sampled alternately, never simultaneously. Gain comes from resistors, not a calibrated attenuator; there is no probe compensation and no isolation from the target’s reference. Switching edges, supply ripple and anything where a hundred nanoseconds matters are out of reach.

It does show audio-band and control signals, provided nobody points it at 20 kHz and believes the answer.

Every figure above comes from the ATmega2560 datasheet and Microchip’s application note at nominal 16 MHz. Actual resolution depends on AVCC decoupling, the reference and your layout, and the front-end values are a starting point, not a validated design.

References

• Microchip, ATmega640/1280/1281/2560/2561 datasheet, section “ADC – Analog to Digital Converter”.
• Microchip, AVR126: ADC of megaAVR in Single-Ended Mode.
• Ilitek, ILI9486 datasheet.
• Solomon Systech, SSD1289 datasheet.